FPGA Programming with Linux

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Short of opening your own chip fab, you can't get much closer to the metal than FPGA programming.
Let's Create New Hardware

In order to show you what it's like to design custom digital hardware and how FPGA development software works, I've modified one of the demo circuits loaded into the Starter Kit, the DNA reader by Xilinx Senior Engineer Ken Chapman.

Spartan FPGAs have a unique ID number, called DNA. The DNA reader displays the intro string “DNA Reader by Ken Chapman”, and then this number is displayed on the LCD screen (Figure 5), working as shown in Figure 6. An Xilinx hardware macro called dna_port reads the DNA ID from the silicon. A PicoBlaze processor first displays the intro string, then gets the DNA ID from dna_port and finally sends it, one character at a time, to the LCD interface through the lcd_d data bus. The PicoBlaze code is stored into the dna_ctrl ROM.

Figure 5. Starter Kit LCD Screen

Figure 6. Simplified Circuit Diagram of the DNA Reader

My modification consists of a small extra circuit that overwrites the default intro string on the fly with one saying “M Fioretti Linux Journal”. Be warned that this is a hack made only for demo purposes. In the real world, if you actually needed to change that string, it would make much more sense to rewrite the PicoBlaze assembly code. Because this is an article about HDL design in FPGAs, however, I went for a solution based on easy-to-read HDL code whose effect is easily visible in one picture.

My extra circuit is shown in red in Figure 6: a counter and decoder that detect when the PicoBlaze is driving the LCD data port (lcd_d) and send different characters to it. The VHDL source code corresponding to this extra hardware is shown in Listing 1, which is not the complete, working VHDL file I used, but only an excerpt meant to give you an idea of how HDL coding works.

Lines 1–12 define input and output ports of the top-level circuit, the reading_dna module. You must declare all internal registers and wires before using them (lines 17–23). HDLs support hierarchy; you can instantiate other modules by declaring them and connecting all their ports to the right signals (lines 26–49). Line 53 shows a first example of a synchronous process. Depending on the value of the cnt_ops counter, whenever there is a positive edge of the clock (line 56) and the processor sets the signals write_strobe and port_id(6) high, the lcd_output_data register loads the character from the processor or the one from my extra logic (lines 62–68). The cnt_and_new_chars process starting at line 80 does the real work. First, it samples the LCD enable signal to count (line 91) the write accesses to the LCD. One cycle after a write occurs, working with the new counter value (line 99), the process calculates the next current_character that should be displayed. If you look at lines 101–125 you'll see that, instead of the DNA number, the display should show the ASCII string “M Fioretti Linux Journal”. A quick simulation (Figure 7) proves that the new process sends those characters to the display at the right times—that is, when the lcd_rs signal is high (low would indicate LCD configuration commands).

Figure 7. Simulation of Listing 1

The procedure to transform this really simple HDL model into properly connected gates on silicon is equally simple. Double-click, one at a time, the icons in the left-center pane of the Project Navigator shown in Figure 1: synthesize, Implement Design, Generate Programming File and Configure Target Device. If you clicked directly on the last one, ISE would do all the previous steps in the right order anyway, but doing it in steps is a better way to learn. Eventually, you'll get the bit file and a final report like the one shown in Figure 8, showing how much silicon was used. Remember, what we just did is actual hardware—that is, transistors directly connected to do, in real time, what we ordered them to do. All that remains to make it actually happen is to load the bit file in the FPGA. Figure 9 shows the result.

Figure 8. Final Output Report

Figure 9. Program Running on FPGA Hardware

______________________

Articles about Digital Rights and more at http://stop.zona-m.net CV, talks and bio at http://mfioretti.com

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richel's picture

hi, how i can download this article, about fpa on linux: article/10330

VHDL, Verilog, SystemC Linux live CD

David Cabanis's picture

Hi guys,

I read your article on FPGA design on Linux. May I suggest you have a look at SCLive. It's a 200 something MB liveCD (can be made persistent on USB stick) dedicated to hardware description languages. It has tutorials on VHDL, Verilog, SystemC and has all the tools (open source) required to start designing with those HDLs.

Don't hesitate to contact me if you need more info.

David Cabanis.
davidcabanis AT gmail DOT com

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