Application Defined Processors

By rebuilding a system's logic on the fly, this project can make one FPGA do the work of tens or hundreds of ordinary processors.
Code Example

To show the performance advantage of a DEL processor, a string-matching example is presented. The code for these examples is available on the Linux Journal FTP site—see the on-line Resources. This example came from the Web site of Christian Charras and Thierry Lecroq, referenced by NIST Dictionary of Algorithms and Data Structures. For comparison, the Brute Force and Boyer-Moore string-matching algorithms are implemented for the 2.8GHz Intel Xeon via Intel's C++ 8.0 compiler for Linux. The Brute Force algorithm is implemented for SRC's system using the Carte 1.8 Programming Environment. The Brute Force algorithm is a straightforward character-by-character comparison between a pattern and a text string. The Boyer-Moore is considered the most efficient string-matching algorithm. The example takes a randomly generated 20MB text string and searches for six and ten randomly generated patterns. Compilations are done with a -O3 optimization setting, and performance comparisons are shown in Table 1. Adding four additional search patterns to the test increases the microprocessor times but has no impact on the MAP execution times due to the pipelined logic. Though the Xeon runs at 2.8GHz, and the MAP runs at 100MHz, the parallelism seen in DEL can achieve a 99× performance advantage in MAP. This example required 60% of one FPGA in the MAP. A two-chip compile would deliver over 200× performance.

Table 1. String-Matching Performance

ImplementationText SizePatternsSearch TimeSpeedup
Brute Force (Xeon)20MB60.827 sec1.00×
Boyer-Moore (Xeon)20MB60.597 sec1.38×
Brute Force (MAP)20MB60.0143 sec57.75×
Brute Force (Xeon)20MB101.398 sec1.00×
Boyer-Moore (Xeon)20MB101.0511.33×
Brute Force (MAP)20MB100.0141 sec98.81×

To demonstrate the impact of adding additional computation into a pipelined loop, and the ability to introduce custom functional units, a second performance comparison is done in which a DES-encrypted string is passed to the search routine. The string must be decrypted prior to searching. In the case of the MAP implementation, a DES pipelined functional unit is introduced. The Verilog definition was obtained from and introduced into the search loop. Because the loop is pipelined, it continues to deliver a set of results per clock cycle. Therefore, the elapsed time for the 20MB text search, including a DES decryption, is unchanged from the search alone. This leads to a very dramatic 232× speedup over the microprocessor implementation. The ten-pattern MAP example uses only 74% of an FPGA, so a two-chip compile for the MAP would yield 460×.

Table 2. Performance for Searching an Encrypted String

ImplementationText SizePatternsSearch TimeSpeedup
DES-Brute Force (Xeon)20MB62.77 sec1.00×
DES-Boyer-Moor (Xeon)20MB62.63 sec1.05×
DES- Brute Force (MAP)20MB60.0143 sec193.09×
DES-Brute Force (Xeon)20MB103.31 sec1.00×
DES-Boyer-Moor (Xeon)20MB103.11 sec1.06×
DES- Brute Force (MAP)20MB100.0143 sec231.76×

In the case of DES implemented on the Xeons, the code is an optimized code by Stuart Levy at Minnesota Supercomputer Center.


This article has explained reconfigurable computing, shown examples of the methods and the results that can be achieved. Significant performance gains can be demonstrated. In the present, RC has much to contribute to computational science, but the future holds advances well beyond the Moore's Law gains experienced in the world of microprocessors. RC is accessible to today's programmers using a familiar programming model and provides the framework within which a larger population of hardware designers can have an impact on high-performance computation through open-source creativity and productivity.

RC has been a long time in coming, but the enabling software and hardware technology has set the stage for RC to become part of every computer, from embedded processor to Peta-Scale supercomputer.

Resources for this article: /article/7867.

Dan Poznanovic ( is VP Software Development at SRC Computers, Inc., and has been involved in the high-performance computing world since initially joining Cray Research, Inc., in 1987.