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FPGA Programming with Linux

Issue 186

From Issue #186
October 2009

Oct 01, 2009  By Marco Fioretti
 in
Short of opening your own chip fab, you can't get much closer to the metal than FPGA programming.
Let's Create New Hardware

In order to show you what it's like to design custom digital hardware and how FPGA development software works, I've modified one of the demo circuits loaded into the Starter Kit, the DNA reader by Xilinx Senior Engineer Ken Chapman.

Spartan FPGAs have a unique ID number, called DNA. The DNA reader displays the intro string “DNA Reader by Ken Chapman”, and then this number is displayed on the LCD screen (Figure 5), working as shown in Figure 6. An Xilinx hardware macro called dna_port reads the DNA ID from the silicon. A PicoBlaze processor first displays the intro string, then gets the DNA ID from dna_port and finally sends it, one character at a time, to the LCD interface through the lcd_d data bus. The PicoBlaze code is stored into the dna_ctrl ROM.

Figure 5. Starter Kit LCD Screen

Figure 6. Simplified Circuit Diagram of the DNA Reader

My modification consists of a small extra circuit that overwrites the default intro string on the fly with one saying “M Fioretti Linux Journal”. Be warned that this is a hack made only for demo purposes. In the real world, if you actually needed to change that string, it would make much more sense to rewrite the PicoBlaze assembly code. Because this is an article about HDL design in FPGAs, however, I went for a solution based on easy-to-read HDL code whose effect is easily visible in one picture.

My extra circuit is shown in red in Figure 6: a counter and decoder that detect when the PicoBlaze is driving the LCD data port (lcd_d) and send different characters to it. The VHDL source code corresponding to this extra hardware is shown in Listing 1, which is not the complete, working VHDL file I used, but only an excerpt meant to give you an idea of how HDL coding works.

Lines 1–12 define input and output ports of the top-level circuit, the reading_dna module. You must declare all internal registers and wires before using them (lines 17–23). HDLs support hierarchy; you can instantiate other modules by declaring them and connecting all their ports to the right signals (lines 26–49). Line 53 shows a first example of a synchronous process. Depending on the value of the cnt_ops counter, whenever there is a positive edge of the clock (line 56) and the processor sets the signals write_strobe and port_id(6) high, the lcd_output_data register loads the character from the processor or the one from my extra logic (lines 62–68). The cnt_and_new_chars process starting at line 80 does the real work. First, it samples the LCD enable signal to count (line 91) the write accesses to the LCD. One cycle after a write occurs, working with the new counter value (line 99), the process calculates the next current_character that should be displayed. If you look at lines 101–125 you'll see that, instead of the DNA number, the display should show the ASCII string “M Fioretti Linux Journal”. A quick simulation (Figure 7) proves that the new process sends those characters to the display at the right times—that is, when the lcd_rs signal is high (low would indicate LCD configuration commands).

Figure 7. Simulation of Listing 1

Listing 1. VHDL Source Code


  1	entity reading_dna is
  2	    Port ( led    : out std_logic_vector(7 downto 0);
  3	           lcd_d  : inout std_logic_vector(7 downto 0);
  4	           lcd_rs : out std_logic;
  5	           lcd_rw : out std_logic;
  6	           lcd_e  : out std_logic;
  7	           j2_30  : out std_logic;
  8	           j2_26  : out std_logic;
  9	           j2_22  : out std_logic;
 10	           j2_14  : out std_logic;
 11	           clk    : in std_logic);
 12	    end reading_dna;
 13	--
 14	architecture Behavioral of reading_dna is
 15	--
 16
 17	-- start extra signals for LJ demo
 18	signal   lcd_e_copy        : std_logic;
 19	signal   lcd_e_del_1       : std_logic;
 20	signal   lcd_e_del_2       : std_logic;
 21	signal   current_character : std_logic_vector(7 downto 0);
 22	signal   cnt_ops           : integer range 0 to 49999999 := 0;
 23	-- end extra signals for LJ demo
 24	begin
 25
 26	  device_dna: dna_port
 27	    port map(   din => dna_din,
 28	               read => dna_read,
 29	              shift => dna_shift,
 30	               dout => dna_dout,
 31	                clk => dna_clk);
 32
 33	  processor: kcpsm3
 34	    port map(      address => address,
 35	               instruction => instruction,
 36	                   port_id => port_id,
 37	              write_strobe => write_strobe,
 38	                  out_port => out_port,
 39	               read_strobe => read_strobe,
 40	                   in_port => in_port,
 41	                 interrupt => interrupt,
 42	             interrupt_ack => interrupt_ack,
 43	                     reset => kcpsm3_reset,
 44	                       clk => clk);
 45
 46	  program_rom: dna_ctrl
 47	    port map(      address => address,
 48	               instruction => instruction,
 49	                       clk => clk);
 50
 51	  kcpsm3_reset <= '0';
 52
 53	  output_ports: process(clk)
 54	  begin
 55
 56	    if clk'event and clk='1' then
 57	      if write_strobe='1' then
 58
 59	        -- 8-bit LCD data output address 40 hex.
 60
 61	        if port_id(6)='1' then
 62	          -- lcd_output_data <= out_port;
 63			  --extra code for LJ demo
 64		      if ((cnt_ops >=  8 and cnt_ops <= 17) or
 65		          (cnt_ops >= 19 and cnt_ops <= 32))  then
 66		        lcd_output_data <= current_character;
 67		      else
 68	            lcd_output_data <= out_port;
 69	          end if; --end extra code for LJ demo
 70	        end if;
 71
 72	      end if;
 73
 74	    end if;
 75
 76	  end process output_ports;
 77
 78	  -- LCD interface
 79
 80	  cnt_and_new_chars: process(clk)
 81	  begin
 82	    if clk'event and clk='1' then
 83
 84		  if port_id(5)='1' and write_strobe='1' then
 85		    lcd_e_copy <= out_port(0);
 86		  end if;
 87
 88	      lcd_e_del_1 <= lcd_e_copy;
 89	      lcd_e_del_2 <= lcd_e_del_1;
 90
 91	      if (lcd_e_copy ='1' and lcd_e_del_1='0') then -- posedge
 92	        if cnt_ops=49999999 then                    -- inc counter
 93	          cnt_ops <= 0;
 94	        else
 95	          cnt_ops <= cnt_ops + 1;
 96	        end if; -- if cnt_ops=49999999
 97		  end if; -- end (lcd_e_copy ='1' and lcd_e_del_1='0')
 98
 99	      if (lcd_e_del_1 ='1' and lcd_e_del_2='0') then  -- posedge
100	        case cnt_ops is                -- character generator
101		    when  8 => current_character <= "01001101"; -- M
102		    when  9 => current_character <= "00100000"; -- space
103		    when 10 => current_character <= "01000110"; -- F
104		    when 11 => current_character <= "01101001"; -- i
105		    when 12 => current_character <= "01101111"; -- o
106		    when 13 => current_character <= "01110010"; -- r
107		    when 14 => current_character <= "01100101"; -- e
108		    when 15 => current_character <= "01110100"; -- t
109		    when 16 => current_character <= "01110100"; -- t
110		    when 17 => current_character <= "01101001"; -- i
111
112		    when 19 => current_character <= "01001100"; -- L
113		    when 20 => current_character <= "01101001"; -- i
114		    when 21 => current_character <= "01101110"; -- n
115		    when 22 => current_character <= "01110101"; -- u
116		    when 23 => current_character <= "01111000"; -- x
117		    when 24 => current_character <= "00100000"; -- space
118		    when 25 => current_character <= "01001010"; -- J
119		    when 26 => current_character <= "01101111"; -- o
120		    when 27 => current_character <= "01110101"; -- u
121		    when 28 => current_character <= "01110010"; -- r
122		    when 29 => current_character <= "01101110"; -- n
123		    when 30 => current_character <= "01100001"; -- a
124		    when 31 => current_character <= "01101100"; -- l
125		    when 32 => current_character <= "00100000"; -- space
126
127		    when others => current_character <= "00100000"; -- space
128
129		    end case;
130	      end if; -- end (lcd_e_del_1 ='1' and lcd_e_del_2='0')
131
132
133	    end if; -- clk'event and clk='1'
134	  end process cnt_and_new_chars;

The procedure to transform this really simple HDL model into properly connected gates on silicon is equally simple. Double-click, one at a time, the icons in the left-center pane of the Project Navigator shown in Figure 1: synthesize, Implement Design, Generate Programming File and Configure Target Device. If you clicked directly on the last one, ISE would do all the previous steps in the right order anyway, but doing it in steps is a better way to learn. Eventually, you'll get the bit file and a final report like the one shown in Figure 8, showing how much silicon was used. Remember, what we just did is actual hardware—that is, transistors directly connected to do, in real time, what we ordered them to do. All that remains to make it actually happen is to load the bit file in the FPGA. Figure 9 shows the result.

Figure 8. Final Output Report

Figure 9. Program Running on FPGA Hardware

______________________

Articles about Digital Rights and more at http://stop.zona-m.net CV, talks and bio at http://mfioretti.com

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get_this_article

richel's picture
Submitted by richel (not verified) on Wed, 06/09/2010 - 09:11.

hi, how i can download this article, about fpa on linux: article/10330

VHDL, Verilog, SystemC Linux live CD

David Cabanis's picture
Submitted by David Cabanis (not verified) on Mon, 09/21/2009 - 17:28.

Hi guys,

I read your article on FPGA design on Linux. May I suggest you have a look at SCLive. It's a 200 something MB liveCD (can be made persistent on USB stick) dedicated to hardware description languages. It has tutorials on VHDL, Verilog, SystemC and has all the tools (open source) required to start designing with those HDLs.

Don't hesitate to contact me if you need more info.

David Cabanis.
davidcabanis AT gmail DOT com

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