man make: a Primer on the Make Utility

Predefined Variables

• $? — evaluates to the list of components that are younger than the current target. Can be used only in description file command lines.

• $@ — evaluates to the current target name. Can be used only in description file command lines.

• $$@ — also evaluates to the current target name. However, it can be used only on dependency lines.

• $< — the name of the related file that caused the action (the precursor to the target). This is only for suffix rules.

• $* — the shared prefix of the target and dependent—only for suffix rules.

Common Variables for C++ Programming

• CC — the name of the compiler.

• DEBUG — the debugging flag. This is -g in both g++ and cxx. The purpose of the flag is to include debugging information into the executable, so that you can use utilities like gdb to debug the code.

• LFLAGS — the flags used in linking. As it turns out, you don't need any special flags for linking. The option listed is -Wall, which tells the compiler to print all warnings. But, that's fine. We can use that.

• CFLAGS — the flags used in compiling and creating object files. This includes both -Wall and -c. The -c option is needed to create object files—that is, .o files.

Suffix Rules

In certain situations, you will find that the rules for a certain file type are identical except for the filename. For instance, a lot of times in a C project, you will see rules like this:

file.o: file.c
        cc -O -Wall file.c

because for every .c file, you need to make the intermediate .o file, so that the end binary then can be built. Suffix rules are a way of minimizing the amount of time you spend writing out rules and the number of rules in your makefile. In order to use suffix rules, you need to tell make which file suffixes are considered significant (suffix rules won't work unless the suffix is defined this way), then write the generic rule for the suffixes. In the case described above, you would do this:

<![CDATA[
.SUFFIXES: .o .c

.c.o:
        cc -O -Wall $<
]]>

You may note that in the case of suffix rules, the dependency suffix goes before the target suffix, which is a reversal from the normal order in a makefile. You also will see that you use $< in the command, which evaluates to the .c filename associated with the .o file that triggered the rule. There are a couple predefined variables like this that are used exclusively for suffix rules:

• $< — evaluates to the component that is being used to make the target—that is, file.c.

• $* — evaluates to the filename part (without any suffix) of the component that is being used to make the target—that is, file.

Note that the $? variable cannot occur in suffix rules, but the $@ variable still will work.

Command Special Characters

Certain characters can be used in conjunction with commands to alter the behavior of make or the command. If you're familiar with shell scripting, you'll recognize that \ signifies a line continuation. That is to say, using \ means that the command isn't finished and continues on the next line. Nobody likes looking at a messy file, and using this character at the end of a line helps keep your makefile clean and pretty. If a rule has more than one command, use a semicolon to separate commands. You can start a command with a hyphen, and make will ignore any errors that occur from the command. If you want to suppress the output of a command during execution, start the command with an at sign (@).

Using these symbols will allow you to make a more usable and readable makefile.

Directives

Sometimes, you need more control over how the makefile is read and executed. Directives are designed exactly for that purpose.

From defining, overriding or exporting variables to importing other makefiles, these directives are what make a more robust makefile possible. The most useful of the directives are the conditional directives though.

Conditional directives allow you to define multiple versions of a command based on preexisting conditions. For example, say you have a set of libraries you want included in your binary only if the compiler used is gcc:

libs_for_gcc = -lgnu
normal_libs =

foo: $(objects)
ifeq ($(CC),gcc)
        $(CC) -o foo $(objects) $(libs_for_gcc)
else
        $(CC) -o foo $(objects) $(normal_libs)
endif

In this example, you use ifeq to check if CC equals gcc and if it does, use the gcc libraries; otherwise, use the generic libraries.

This is just a small, basic sampling of the things you can do with make and makefiles. There are so many more complex and interesting things you can do, you just have to dig around to find them!

Resources

GNU make comes with most Linux distributions by default, but it can be found on the main GNU FTP server: http://ftp.gnu.org/gnu/make (via HTTP) and ftp://ftp.gnu.org/gnu/make (via FTP). It also can be found on the GNU mirrors at http://www.gnu.org/prep/ftp.html.

Documentation for make is available on-line at http://www.gnu.org/software/make/manual, as is documentation for most GNU software. You also can find more information about make by running info make or man make, or by looking at /usr/doc/make/, /usr/local/doc/make/ or similar directories on your system. A brief summary is available by running make --help.