Porting LinuxBIOS to the AMD SC520: A Follow-up Report
We now get this output:
Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-18.104.22.168Fallback Wed Jun 22 16:10:58 MDT 2005 booting... Enumerating buses... scan_static_bus for Root Device PCI_DOMAIN: 0000 enabled scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 missing read_resources Root Device read_resources bus 0 link: 0 done Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0e Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 missing read_resources Root Device read_resources bus 0 link: 0 done Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: e Done reading resources. Setting resources... Root Device compute_allocate_io: base: 00001000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 missing read_resources Root Device read_resources bus 0 link: 0 done Root Device compute_allocate_io: base: 00001000 size: 00000000 align: 0 gran: 0e Root Device compute_allocate_mem: base: 100000000 size: 00000000 align: 0 gran:0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 missing read_resources Root Device read_resources bus 0 link: 0 done Root Device compute_allocate_mem: base: 100000000 size: 00000000 align: 0 gran:e Root Device assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resources... PCI_DOMAIN: 0000 missing enable_resources done. Initializing devices... Root Device init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Wrote LinuxBIOS table at: 00000500 - 00000af0 checksum 934c Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 23:stream_init() - rom_stream: 0xffff0000 - 0xffff7fff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 Could not find a bounce buffer... Cannot Load ELF Image
Well, that's a start anyway. What's up with the bounce buffer? This is not the real problem. The real problem is LinuxBIOS thinks there is no memory. Remember that in the beginning we set up the CPU with no functions to be called? It turns out we do need to have some functions called, because part of what the functions have to do is indicate how much memory there is. We can look to another Northbridge chip for inspiration. It is pretty close to the SC520 and avoids the complications of the K8 Northbridge, which are very complex. You can see how things now look in the repository, at version 50.
We get a FILO banner and an immediate reset, but at least we get something. Now it's time to turn up the debugging in FILO and see what's wrong.
It turns out that this chip has no hardware timestamp counter (TSC). So when you try to read the TSC, the chip does the right thing; namely, it takes a general protection fault and goes into crash-and-burn mode. FILO never has run before on a chip without a TSC. We had to fix FILO.
We've included a FILO in the Subversion version of the LinuxBIOS tree that can use the SC520 millisecond timer. This timer is a nice free-running timer that provides an accurate timestamp count.
Once we do that, FILO gives us a prompt but says there is no IDE. Another trip back to the MMCR registers shows we need to enable the built-in IDE chip select lines, which are not on by default. Oddly enough, a lot of these embedded chips with built-in controllers tend to come up with those features disabled. Setting a few more MMCR registers by hand does the trick.
As of June 28, we have been booting a Linux kernel. A few more registers needed to be set and then we were good to go.
The kernel comes up and works fine, except not all the interrupts are getting to it. This is a problem in the configuration of the interrupt registers. The interrupt registers are located in the MMCR region of memory, which we previously have had to deal with. Our first idea was to simply dump the registers and restore them, but doing so only made things worse! At that point, not even the clock interrupt worked. Obviously, there is some trickiness to the interrupt register settings that we need to work out.
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