MyHDL: a Python-Based Hardware Description Language

MyHDL supports waveform viewing, a popular way to visualize hardware behavior. In Listing 2, the instantiation of the SPI slave module is wrapped in a call to the function traceSignals. As a side effect, signal changes are dumped to a file during simulation, in a standard format. Figure 1 shows a sample of the waveforms rendered by gtkwave, an open-source waveform viewer.

Figure 1. Using gtkwave, you can visualize all the signals as the test suite runs.

MyHDL is a practical solution with links to other HDLs. MyHDL supports co-simulation with other HDL simulators that have an interface to the operating system. A bridge must be implemented for each simulator. This has been done for the open-source Verilog simulators Icarus and cver.

In addition, an implementation-oriented subset of MyHDL code can be converted automatically into Verilog. This is done with a function called toVerilog, which is used in the same way as the traceSignals function described earlier. The resulting code can be used in a standard design flow, for example, to synthesize it automatically into an implementation.

Tim Peters, a famous Python guru, explains his love for Python with the paradoxical statement, “Python code is easy to throw away.” In the same spirit, MyHDL aims to be the hardware design tool of choice to experiment with new ideas.

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