MyHDL: a Python-Based Hardware Description Language
The SPI slave module was modeled at a level that stays close to an actual implementation. This is a good way to introduce MyHDL's concepts. However, using MyHDL for this purpose doesn't provide a lot of advantages over traditional HDLs. Instead, MyHDL's real value is it makes the whole of Python available to hardware designers. Python's expressive power, flexibility and extensive library offer possibilities beyond the scope of traditional HDLs.
One area in which Python-like features are desirable is verification. As with software, in hardware design, verification is the hard part. It generally is acknowledged that traditional HDLs are not up to the task. Consequently, yet another language type has emerged, the hardware verification language (HVL). Once again, MyHDL relies on Python to challenge this trend.
To set up a hardware verification environment, we first create a test bench. This is a hardware module that instantiates the design under test (DUT), together with data generators and checkers. Listing 2 shows a test bench for the SPI slave module. It instantiates the SPI slave module together with an SPI tester module that controls all interface pins. To be able to use multiple SPI tester modules that verify various aspects of the design, the SPI tester module is a parameter of the test bench.
Listing 2. A Test Bench for the SPI Slave Module
import unittest from random import randrange from myhdl import Signal, intbv, traceSignals from SPISlave import SPISlave, ACTIVE_n, INACTIVE_n def TestBench(SPITester, n): miso = Signal(bool(0)) mosi = Signal(bool(0)) sclk = Signal(bool(0)) ss_n = Signal(INACTIVE_n) txrdy = Signal(bool(0)) rxrdy = Signal(bool(0)) rst_n = Signal(INACTIVE_n) txdata = Signal(intbv(0)[n:]) rxdata = Signal(intbv(0)[n:]) SPISlave_inst = traceSignals(SPISlave, miso, mosi, sclk, ss_n, txdata, txrdy, rxdata, rxrdy, rst_n, n=n) SPITester_inst = SPITester( miso, mosi, sclk, ss_n, txdata, txrdy, rxdata, rxrdy, rst_n, n=n) return SPISlave_inst, SPITester_inst
For the tests themselves, we use a unit testing framework. Unit testing is a cornerstone of extreme programming (XP), a modern software development methodology that is an intriguing mixture of common sense and radically new ideas. The genuine XP approach is to develop the test first, before the implementation. XP is a useful methodology, but its lessons virtually are ignored by the hardware design community. With MyHDL, Python's unit testing framework, unittest, can be used for test-driven hardware development.
Listing 3 shows test code for the SPI slave module. Tests are defined in a subclass of the unittest.TestCase class. Each method name with the prefix test corresponds to an actual test, but other methods can be written to support the tests. A typical test suite consists of multiple tests and test cases, but we describe a single test to demonstrate the idea.
Listing 3. A Test Case for Receiving Data via SPI
import unittest from random import randrange from myhdl import Simulation, join, delay, \ intbv, downrange from SPISlave import SPISlave, ACTIVE_n, INACTIVE_n from SPISlaveTestBench import TestBench n = 8 NR_TESTS = 100 class TestSPISlave(unittest.TestCase): def RXTester(self, miso, mosi, sclk, ss_n, txdata, txrdy, rxdata, rxrdy, rst_n, n): def stimulus(data): yield delay(50) ss_n.next = ACTIVE_n yield delay(10) for i in downrange(n): sclk.next = 1 mosi.next = data[i] yield delay(10) sclk.next = 0 yield delay(10) ss_n.next = INACTIVE_n def check(data): yield rxrdy self.assertEqual(rxdata, data) for i in range(NR_TESTS): data = intbv(randrange(2**n)) yield join(stimulus(data), check(data)) def testRX(self): """ Test RX path of SPI Slave """ sim = Simulation(TestBench(self.RXTester, n)) sim.run(quiet=1) if __name__ == '__main__': unittest.main()
The RXTester method is a generator function designed for a basic test of the SPI slave receive path. It contains a local generator function, stimulus, that transmits a data word on the SPI bus as a master. Another local generator function, check, checks whether the data word is received correctly by the slave. The complete test consists of a number of random data word transfers. For each data word, we create a stimulus and a check generator. To wait for their completion, MyHDL allows us to put them in a yield statement. For proper synchronization, we want to continue only when both generators have completed. This functionality is accomplished by the join function.
When we run the test program, the output indicates which tests fail at what point. When everything works, the output from our small example is as follows:
$ python test_SPISlave.py -v Test RX path of SPI Slave ... ok ------------------------------------------------ Ran 1 test in 0.559s
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