MyHDL: a Python-Based Hardware Description Language
Having introduced the concepts, we now are ready to tackle a real design example with MyHDL. I have chosen a serial peripheral interface (SPI) slave hardware module. SPI is a popular synchronous serial control interface originally designed by Motorola.
A single SPI master can control multiple slaves. There are three common I/O ports: mosi, the master-out, slave-in serial line; miso, the master-in, slave-out serial line; and sclk, the serial clock driven by the master. In addition, a slave select line, ss_n, exists for each slave. SPI communication always occurs in the two directions simultaneously. In general, the active clock edge that triggers data changes is configurable. In this example, we use the rising edge.
The MyHDL code of the SPI slave is shown in Listing 1. A classic Python function called SPISlave is used to model a hardware module. The function has all interface signals as its parameters, and it returns two generators. This code illustrates how hierarchy is modeled in MyHDL: a higher-level function calls lower-level functions and includes the returned generators in its own return value.
Listing 1. MyHDL Model of an SPI Slave
from myhdl import Signal, posedge, negedge, intbv ACTIVE_n, INACTIVE_n = bool(0), bool(1) IDLE, TRANSFER = bool(0), bool(1) def toggle(sig): sig.next = not sig def SPISlave(miso, mosi, sclk, ss_n, txdata, txrdy, rxdata, rxrdy, rst_n, n=8): """ SPI Slave model. miso -- master in, slave out serial output mosi -- master out, slave in serial input sclk -- shift clock input ss_n -- active low slave select input txdata -- n-bit input with data to be transmitted txrdy -- toggles when new txdata can be accepted rxdata -- n-bit output with data received rxrdy -- toggles when new rxdata is available rst_n -- active low reset input n -- data width parameter """ cnt = Signal(intbv(0, min=0, max=n)) def RX(): sreg = intbv(0)[n:] while 1: yield negedge(sclk) if ss_n == ACTIVE_n: sreg[n:1] = sreg[n-1:] sreg = mosi if cnt == n-1: rxdata.next = sreg toggle(rxrdy) def TX(): sreg = intbv(0)[n:] state = IDLE while 1: yield posedge(sclk), negedge(rst_n) if rst_n == ACTIVE_n: state = IDLE cnt.next = 0 else: if state == IDLE: if ss_n == ACTIVE_n: sreg[:] = txdata toggle(txrdy) state = TRANSFER cnt.next = 0 else: # TRANSFER sreg[n:1] = sreg[n-1:] if cnt == n-2: state = IDLE cnt.next = (cnt + 1) % n miso.next = sreg[n-1] return RX(), TX()
The module interface contains some additional signals and parameters. txdata is the input data word to be transmitted, and txrdy toggles when a new word can be accepted. Similarly, rxdata contains the received data word, and rxrdy toggles when a new word has been received. Finally, there is a reset input, rst_n, and a parameter n that defines the data word width.
Inside the SPI slave module, we create a signal, cnt, to keep track of the serial cycle number. It uses an intbv object as its initial value. intbv is a hardware-oriented class that works like an integer with bit-level facilities. Python's indexing and slicing interface can be used to access individual bits and slices. Also, an intbv object can have a minimum and a maximum value.
The RX generator function describes the receive behavior. Whenever the slave select line ss_n is active low, the mosi input is shifted to the shift register sreg. The yield negedge(sclk) statement indicates that the action occurs on the falling clock edge. In the last serial cycle, the shift register is transferred to the rxdata output and rxrdy toggles.
The TX generator function is slightly more complicated, because it requires a small state machine to control the protocol. The yield statement specifies two events in this case, meaning that the generator is resumed on the event that occurs first. When the reset input is active low, cnt and state are reset. In the other case, the action depends on the state. In the IDLE state, we wait until the select line goes active low before accepting the data word for transmission and going to the TRANSFER state. In the TRANSFER state, the shift register is shifted out serially. The state machine maintains the proper serial cycle count and returns to the IDLE state on the last shift.
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