Xilinx FPGA Design Tools for Linux
With the Verilog entered, as shown in Listing 1, we start synthesis by double-clicking on the Synthesize - XST button in the Project Navigator tool scroll list. This design we've entered is easy to synthesize and takes only a few moments. The synthesis results can be viewed by reading the synthesis report file (Figure 7). The check marks in the tool scroll list at the left indicate what Project Navigator accomplished. The synthesis report file is in the upper right. You can look through this to see how XST decided to infer your logic to the target FPGA, as well as glean an estimated clock-rate performance for the resulting design in that FPGA.
RTL is a view of your logic as various black boxes or logic gates that are situated between flip-flop registers. RTL is the predominant view of logic in synchronous design. The View RTL Schematic button in the ISE 6.1i tools offers an excellent way to get a graphical overview (Figure 8). You can navigate across any hierarchy of modules in your design with the RTL schematic being regenerated dynamically. We're now ready to run the FPGA implementation tools.
We start implementation by clicking Implement Design in the tool list at the left in Project Navigator. For FPGA implementation, the generic process automatically engaged by the tools goes as follows: translate, map and place and route.
In most cases with FPGA design, you do not need to know the specifics of the operation of these steps, with the exception of seeking extremely high performance from the FPGA. But it can be helpful to know what's going on. For example, map determines how the inferred synthesis results get “mapped” to your selected target FPGA. Looking at the map report file can provide useful information about the allocation of resources. Similarly, sometimes it can be useful to read the place and route (PAR) report file to learn whether options are available to improve the speed of your design or to constrain resource utilization more carefully earlier in the toolchain.
Other tools in ISE 6.1i not encountered in this article provide much flexibility for performance engineering and for creating constraints such as locking the FPGA I/O pins for subsequent use with PCB boards, given iterative FPGA implementation to fix bugs.
This design used only one out of the 44 available multipliers on the xc2vp7 FPGA. Also indicated are the 65 I/O pins that were requested for this logic. The Pad report generated by the tool will tell you which FPGA pins were selected in implementation. As mentioned above, you also can preselect these pins for a board design, and this is done with a constraint editor in the tool or by creating a constraint file.
FPGAs are fast CMOS devices. It's important for us to know how fast, in order to verify static timing goals against system requirements. Other important information for system design might include knowing setup time information or clock-to-pin delays. ISE 6.1i provides an integrated timing analyzer. A timing report file can be generated automatically, based on all routing and propagation delays for the completed implementation in the target FPGA.
You also can look inside the FPGA device by clicking the FPGA editor tool after implementation. This tool opens a separate screen (Figure 9). The initial view is a called a worldview, where you can see your whole FPGA at once. As you probably can see in the center view, very little of the 2vp7 was used. This view becomes quite dense with high-utilization designs. The large block in the view is the PowerPC microprocessor. Also visible are other multiplier blocks, block RAMs and numerous other elements in the FPGA. Various blocks in the design can be highlighted selectively.
The last step in FPGA implementation is bitgen, or bit generation of the configuration bitstream for the FPGA so that the device can be programmed in a system. After pressing Generate Programming File, the bitstream is created automatically from the FPGA implementation data. The bitgen tool creates a report file, which is shown in Figure 10, in the upper right.
After creating the FPGA bitstream, there are numerous options for using it to create programming files. These depend a lot on the hardware mechanism you want to use for programming the FPGA. The options include PROM file, ACE file, JTAG file and direct configuration of the FPGA.
PROM files are used for conventional PROM programmers, for example, to make an EPROM that goes in your system. ACE files are used with the Xilinx SystemACE CF programming solution. SystemACE CF is a low-cost way to embed a CompactFlash device in your system. Using ACE files, you can create data on a conventional CompactFlash card that can be used for FPGA configuration, dynamic reconfiguration and multiple-device configuration. You also can boot the PowerPC processor this way.
JTAG files are used with Xilinx download cables over a JTAG chain for the FPGA device(s) in your system. JTAG enables configuration, control and bitstream or debugging feedback. In particular, JTAG is the primary mechanism for the Xilinx ChipScope Pro 6.1i tool, which is an integrated logic analyzer that gets embedded into your on-chip logic for live in situ hardware debugging. You also can configure the programming of the FPGA directly from a PC, using the iMPACT tool and a download cable.
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