Xilinx FPGA Design Tools for Linux
A field programmable gate array (FPGA) is a user-programmable piece of silicon constructed in very large-scale integration (VLSI) technology. The VLSI transistor-level detail is absolutely predefined in an FPGA. Internally, the FPGA consists of a matrix-like fabric of logic and interconnect elements that are inherently flexible. Flexibility is accomplished through programmable SRAM memory cells that define the silicon resources. FPGAs are standard commodity parts with trillions of possible user configurations. This essential organizational structure of the FPGA has persisted through two decades of VLSI technology development. However, today's FPGAs are utterly unlike those of yesteryear.
FPGAs are blurring the lines between hardware and software in systems. FPGA devices are inherently soft-programmable and may be changed dynamically during the operation of a system. More compellingly, FPGA devices now also contain embedded microprocessors within the logic fabric, and these microprocessors can run Linux. Imagine a Linux computer with up to millions of gates of flexible logic immediately around it. One way to grok this new paradigm is to think of the following: “Software is configuration bits for hardware.”
FPGA design is custom silicon design with less effort than full-custom VLSI design. Besides processor cores, FPGAs today not only have logic gates and flip-flops, they also have large Block RAMs, embedded hardware multipliers, arithmetic acceleration logic, digital clock managers (DCMs) for frequency synthesis, multistandard system I/O cells with programmable line termination and multi-gigabit transceivers (MGTs). These system-oriented resources, along with the kinds of device packages and user I/O counts, are enumerated in Figure 1, which shows the most advanced of the FPGA devices, the Xilinx Virtex-II Pro family.
The technology of VLSI memory is everything in this equation—FPGAs are in the realm of commodity silicon manufacturing and typically have better silicon wafer yields than custom VLSIs. Following Moore's Law, FPGAs, much like DRAM and other advanced memory products, are the lead silicon technology drivers, pushing the most advanced 300mm wafer technology at deep submicron densities.
In this article, we introduce the most recent Xilinx FPGA design tools. The design tools are called the Integrated Software Environment, or ISE. These design tools are now released for the Linux platform as the Xilinx ISE 6.1i tools for Linux. This allows FPGA design on a platform having very low total cost of ownership.
Designing with an FPGA device is both different from and similar to programming microprocessors in a language such as C. Hardware description languages (HDLs) are used to design logic at a high level. Verilog and VHDL are the most popular HDLs in industry practice, and ISE 6.1i supports both. These languages allow description of hardware in structural or behavioral terms, or as a mix of both. HDLs are the input source code for specialized compilers, which either synthesize logic for a target or allow it to be simulated. Here, our focus is on logic synthesis, with an inside look at the FPGA and, finally, generation of the configuration bitstream with the ISE 6.1i tools.
One way logic is different from software is that it's inherently parallel. HDLs can describe numerous concurrent changes directly, unlike the major programming languages, for example, when specifying synchronous changes in a logic circuit based on the rising edge of a clock signal. In logic design, as contrasted with programming, one is often describing something that takes area, not memory. Both logic and programs require that time elapses during operation, and our preference is normally that it be very little time. As we will see, the ISE 6.1i design tools can help with both area and time optimization.
This article covers the basic steps in entering a simple but interesting design in Verilog and explores some of the capabilities of the tool. We also look inside the FPGA device configuration. See Resources for more information about the Verilog HDL. Additionally, refer to the July 2002 issue of LJ (/article/6001) for an article on a free Verilog tool, which also contains a Verilog tutorial.
For this tour, we synthesize a 16-bit pipelined parallel multiplier by specifying it with behavioral Verilog. We use synthesis to create and evaluate this result. Then, we use the implementation tools in ISE 6.1i to create a configuration for a particular Virtex-II Pro FPGA device. Various options of the toolchain are explained in the process, including a way to look inside the implemented FPGA.
After the software is installed, we open a shell and begin. The process starts by typing ise at the command line. This brings up the Project Navigator, which is the screen shown in Figure 2. To start a new FPGA design project, select a new project under the File menu. This brings up the window shown in Figure 3. Here, we enter a project name, MPY-TEST, and indicate the kind of top-level module we're going to use for this project. We are interested in an HDL top-level module for this tour, but ISE 6.1i allows the use of several other top-level module types.
Practical Task Scheduling Deployment
July 20, 2016 12:00 pm CDT
One of the best things about the UNIX environment (aside from being stable and efficient) is the vast array of software tools available to help you do your job. Traditionally, a UNIX tool does only one thing, but does that one thing very well. For example, grep is very easy to use and can search vast amounts of data quickly. The find tool can find a particular file or files based on all kinds of criteria. It's pretty easy to string these tools together to build even more powerful tools, such as a tool that finds all of the .log files in the /home directory and searches each one for a particular entry. This erector-set mentality allows UNIX system administrators to seem to always have the right tool for the job.
Cron traditionally has been considered another such a tool for job scheduling, but is it enough? This webinar considers that very question. The first part builds on a previous Geek Guide, Beyond Cron, and briefly describes how to know when it might be time to consider upgrading your job scheduling infrastructure. The second part presents an actual planning and implementation framework.
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