An Introduction to IC Design Under Linux
To see which components are connected to a particular rectangle, place the cursor over it and press the s key twice quickly. The first key press selects the rectangle; the second selects everything that's electrically connected to it. Try this on either metal rail, and notice that they are both electrically isolated from everything else. The top rail must connect to the diffusion on one side of the PFET and the bottom rail to the diffusion on one side of the NFET; otherwise, no current can flow. Thus, we need what's called a diffusion-to-m1 contact, abbreviated pdc or ndc depending on whether we're talking about p or n diffusion respectively.
Place the box at ll=(0,5), ur=(4,9) and type :pai ndc. Now make a pdc at ll=(0,19) and ur=(4,27). Checking connectivity shows that the rails are connected to both the adjacent contacts and the diffusion right up to, but not including, the transistor. At this point, check your layout against Figure 4.
Now for the output. In a CMOS inverter, the output is made by connecting together the sides of the transistors that are not connected to a rail. Place the box at ll=(8,5) and ur=(12,9) and paint an ndc (try doing this using the middle mouse button). Then put the box at ll=(8,19) and ur=(12,27) and paint a pdc. To connect these two contacts together, we need m1 between them: put the box at ll=(8,9) and ur=(12,19) and paint m1. Check the connectivity of the output to verify that the two contacts are tied together.
Congratulations. You've just drawn the layout for a fully-functional CMOS logic gate—however, we're not quite finished.
Labeling assigns a name to a specified rectangle in the layout and thereby to every rectangle electrically connected to it. Labeling serves two purposes. First, it's like commenting code in that it lets you know what signals are where. Second, it makes simulation much easier when you pick sensible names rather than generate them automatically; for automatically, “input” is much easier to remember than “a_43_n15#”.
Let's label the rails first. Select the upper rail by moving the cursor over it and pressing the s key. Then type:
“Vdd” should appear next to the rail. Select the other rail and type :lab Gnd. Notice the labels are placed somewhat randomly. Now select the poly between the two transistors and type :lab in center. This places the label in the middle of the selected rectangle. Finally, select the output m1 and type :lab out center. The now-finished layout should look like Figure 5.
To save your layout, type :save. If you want to save it under another name, simply type the name too; e.g., :save newcellname. Magic automatically appends a .mag extension.
The next step is to simulate the layout to verify that it works correctly. Magic's .mag files are stored simply as a collection of various types of rectangles, but simulators require a netlist of circuit components, such as transistors and capacitors. Recall that a netlist is a list of circuit components and how they're connected.
You use Magic itself to extract a netlist from a layout. Magic's extractor recognizes various combinations of rectangles as defined in the tech file and converts them into the appropriate circuit elements. It also extracts connectivity between shapes, thus making a complete netlist.
You must choose an “extraction style”, which tells Magic how to interpret the shapes in the layout. To see the available styles, type :extract style. For our purposes, the important part of the style name is the number, which refers to the minimum transistor length. For example, in the lambda=1.0(scna20_orb) style we'll use, this length is 2.0mm. This should be the current style; if it's not, enter:
:extract style lambda=1.0(scna20_orb)
To complete the extraction, simply type :extract. Magic makes an inverter.ext file. This file is an intermediate description of the circuit containing all the information necessary to build a netlist for various simulators. We're now ready to begin simulation, so quit magic by entering :quit.
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